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	Andy Glew's Resume
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	<BIG>
	Andy Glew
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	<center>
	412 West Shore Drive <br>
	Madison, WI 53715 <br>
	<br>
	Home: 503-693-9830
	<br>
	<code>
	glew@cs,wisc.edu
	glew@ichips.intel.com
	</code>
	</center>


	<h2>Career Goals</h2>
	    <ul>
		<li>Challenging hardware/software development.
		<li>To design the next generation of 
		    high-performance microprocessor,
		    going beyond out-of-order dynamic execution
		    and instruction level parallelism
		    towards meso-scale parallelism.
		<li>To apply the technical management concepts
		    that can create a "Breakthrough System" 
		    for creative work like Computer Architecture;
		    to recreate Thomas Edison's "Invention Factory"
		    in the modern world.
	    </ul>


	<h2>Skills</h2>

	    <dl>
	    <dt><b>Performance Tuning and Analysis</b><dd>
		<ul>
		<li>Both hardware and software.
		<li><em>I can make anything run faster!</em>
		</ul>
	    <dt><b>Hardware</b><dd>
		<ul>
		<li>High-performance computer architecture,
		    especially out-of-order microarchitectures.
		<li>Parallel processors 
		<li>Synchronization 
		<li>Cache and Bus Protocols 
		<li>Memory Consistency Models 
		<li>Super-scalar Processors 
		<li>Behavioural and structural modelling in 
		    RTLs (register transfer languages)
		    such as iHDL (Intel Hardware Description Language).
		<li>Computer arithmetic,
		    particularly redundant forms to increase performance.
		</ul>
	    <dt><b>Software</b><dd>
		<ul>
		<li>OS: UNIX System V and BSD 4.3 kernel. Some NT kernel. 
		    Win95 drivers.
		<li>Programming Languages: C, LISP used regularly. 
		    Familiar with C++, COBOL, FORTRAN, PASCAL, PL/1. 
		<li>Assembly Languages: 680x0, 88K, 80x86, Gould PN and NP, MIPS R2000,
		    PowerPC.
		<li>Environments: super-micro to mini-super.
		</ul>
	    </dl>


	<h2>Education</h2>

	    <ul>
	    <li>August 1996 - date:
		Ph.D. student at the University of Wisconsim, Madison.
		Advisor: Guri Sohi.
		<!WA0><!WA0><!WA0><A HREF="http://www.cs.wisc.edu/~glew/generic-PhD-research-interests.html">
		Research interests:
		</A>
		    more aggressive out-of-order,
		    superscalar, dynamic execution, CPUs. 
	    <li>September 1987 - January 1991: 
		University of Illinois at Urbana Champaign, 
		M.Sc. in Electrical and Computer Engineering. 
		Thesis: "Synchronization Primitive Implementation 
		    including the Bus Abandonment Lock" 
		Advisor: Wen-mei Hwu. 
		Subject area: computer architecture, parallel processing, 
		    synchronization  instructions, 
		    cache and bus protocols. 
		Other research: super scalar processing (register 
		    renaming, minimal control dependencies).
		Part time before January 1990 
		(while working at Gould and Motorola). 
		GPA 4.8/5.

	    <li>1980-1985: McGill University, Montreal, 
		Bachelor of Engineering in Electrical Engineering 
		    (Computer Option). 
		GPA 2.87/4. 
		Projects include: 
		    RAMM/RISC/SEISM - a Reduced Addressing Mode, RISC, 
			Small Efficient Instruction Set Machine.

	    <li>1978-1980: Marianopolis College, Montreal, 
		Diplome des Etudes Collegiales.

	    </ul>




	<h2>Employment</h2>


	    <dl>

	    <dt>January 1991-date: Intel Corporation, Hillsboro, Oregon<dd>

		<P>

		<DL>

		<dt>August 1996-date: <b>Student</b><dd>
		    Although I continue to be affiliated with Intel's Microcomputer Research Labs
		    - e.g. I am still covered by the Intel NDA, and will work at Intel on breaks -
		    I am now mainly a full time student pursuing my Ph.D.


		<dt>November 1995-August 1996: <b>Computer Architect/Researcher</b>,
		    Microcomputer Research Labs; Leader, Intel Architecture
		    CPU Research Group<dd>

		    <P>
		    <B>Manager</B>: Richard Wirt (Intel Fellow).
		    </P>

		    <p>
		    I agreed tp spend approximately one year 
		    (prior to returning to school to finish my Ph.D.)
		    helping to get this research group
		    off the ground, 
		    defining the research directions
		    hiring 5 Ph.D. level researchers (and trying to hire more),
		    and budgetting and arranging capital purchases of approximately
		    500,000$ in computer equipment and services.
		    <p>


		<dt>January 1991-November 1995: <b>Computer Architect</b>, P6.<dd>

		    <P>
		    <B>Managers</B>: Bob Colwell (1991-1993), Dave Papworth (1993-1995).
		    </P>

		    <ul>
		    <li>One of five architects involved in the 
			<B>Original P6 Microarchitecture Definition</B>
			(in 1991)
			and supported design by providing oversight 
			and making global tradeoffs throughout the life of the project.
			<ul>
			<li>Defined top-level interface between subsystems.
			<li>Defined execution unit "uop" instruction set.
			<li>Defined microcode format.
			<li>Significant contributions to design of
			    non-blocking cache.
			<li>Defined and performed initial RTL coding of branch mechanism, 
			    including interfaces between BTB and execution units.
			<li>Simulation studies to simplify logic involved in 
			    retirement of branches.
			<li>Defined global control register bus.
			</ul>
		    <li>After initial definition phase led 
			<B>P6 HW/SW Codevelopment</B> team 
			(up to 3 full time engineers, 3 students)
			<ul>
			<li>Wrote <B>P6 External Architecture Specification.</B>
			    Defined all new architecturally
			    visible features (Machine Check,
				mechanisms for reducing TLB invalidations, 
				memory types)
			    and new instructions
				(conditional moves, fast system calls).
			<li>Liaison between P6 Architecture and software groups:
			    <B>compilers</B>, <B>OSes</B> (Intel and Microsoft), 
			    assembly language applications such as 
			    <B>
			    multimedia, 
			    video,
			    3D graphics, and games </B>
			    developers.
			<li>Wrote <B>P6 Code Tuning</B> Guide.
			<li>Defined new memory types that increase memory to <b>framebuffer</b>
			    performance by 4-7X.
			<li>Defined and supervised <b>block memory fill and copy optimizations</b>,
			    including inventing a new cache protocol that reduces memory
			    traffic by 50-30%.
			<li><B>Tuned code</B>,
			    including a single, notorious, optimization that improved
			    iSPEC92 by approximately 25%.
			    Supervising recent work improving branch predictability.
			    Supervising much work improving performance analysis tools
			    for code tuning.
			<li>Defined P6 <B>Performance Monitoring</B> hardware (EMON).
			    Defined and supervised development of software 
			    (UNIX and Windows)
			    to perform 
			    <B>EMON profiling</B>, a new method of performance analysis
			    involving statistical sampling of code locations associated
			    with particular performance problems.
			<li>Defined and supervised development of
			    <B>Priviliged Mode Execution (PMX)</B> 
			    device driver, on UNIX on Microsoft OSes,
			    permitting access to many hardware priviliged facilities 
			    from user code,
			    facilitating automation of many performance and validation
			    testing procedures.
			<li>Initially defined and supervised development of
			    <B>API Profiling</B> device drivers on Windows 3.1,
			    which permitted investigation of performance issues
			    not just by flat code location, but also according to call tree.
			    Supervised first application of this tool to tuning 
			    computer games and 3D graphics applications.
			</ul>
		    <li>Acted as an x86 architecture expert,
			frequently representing P6 to 
			Intel's <B>Compatibility Architecture Review Team (CART).</B>
			<ul>
			<li>Creator and keeper of the official Intel x86 Instruction Set
			Definition, on behalf of CART.
			<li>CART expert on APIC (interrupt controller) architecture.
			<li>CART expert on SMM (System Management Mode).
			</ul>
		    <li>Original investigator of x86 instruction set
			enhancements to support multimedia, video, and graphics;
			P6 representative on <B>MMX</B> definition effort;
			key inventions that permit instruction set enhancement
			without OS changes.
		    <li>P6 representative in evaluation 
			of future instruction set architectures.
		    <li>Future x86 microarchitectures.
		    <li>Member of Intel Research Council's 
			Natural Datatypes Technical Committee, supervising research
			in multimedia, graphics, speech and handwriting recognition, etc.
		    </ul>
		</DL>
		</P>

	    <dt>January 1990-May 1990: <b>Teaching Assistant</b>
		Foundations for <b>VLSI Design</b> Automation<dd>
		<P>
		Course CS497-LGJ 
		taught by Professor Larry Jones, 
		at AT&T Bell Labs Naperville (Indian Hill). 
		University of Illinois at Urbana-Champaign, 
		Department of Computer Science.
		</P>

	    <dt>December 1985-November 1989: <b>OS Developer</b><dd>

		<p>
		From December 15 1985 to November 15 1989 
		I was a member of the technical staff 
		at 1101 E. University, Urbana, IL 61801. 
		Before October 7, 1988, the site was owned by Gould CSD. 
		On October 7, 1988, the site was sold to Motorola MCD. 
		On November 15, 1989, I left to take a vacation 
		before returning to full-time studies 
		in January 1990.
		</p>

		<ul>
		<li>October 1988-October 1989: 
		    <b>Performance Evaluation Team Leader</b>, 
		    Motorola Microcomputer Division, 
		    manufacturer of MC680[234]0 and MC88000 VME bus computer systems 
		    based on AT&T UNIX System V release 3. 
		    Tasked to "find the next generation of computer system 
		    performance problems". 
		    Worked widely in UNIX kernel and VMEbus board level 
		    performance issues.

		    <ul>
		    <li>Supervised one computer scientist, 
			working in filesystem performance, 
			leading to multiple filesystem block sizes, 
			and a change in buffer cache scanning algorithm 
			to improve interactive response. 
		    <li>Wrote kernel tuning guide for SYSTEM V/68 systems. 
		    <li>Investigated poor memory system performance 
			due to insufficient write buffering 
			and slow bus arbitration. 
		    <li>Wrote white paper on timers, 
			leading to an improved comparison based timer 
			implemented in 68040 systems 
			that eliminated jitter and drift errors. 
		    <li>Consultant to Multiprocessor and Graphics groups. 
		    <li>Devised performance tests for interactive "jerkiness". 
		    <li>Budgetted for approximately 50,000$US 
			of hardware and software resources and 
			purchases.
		    </ul>

	    <li>December 1985 - October 1988: <b>Member of Technical Staff</b>, 
		    Gould Computer Systems Division, 
		    Urbana, Illinois, 
		    manufacturer of Gould PN superminis and NP minisupers. 
		    Advanced Planning: 
			Active in discussions and planning 
			for advanced RISC mini-supercomputer systems. OS group 
			interface to hardware design. Instruction set retirement, 
			interrupt structure simplification.


			<ul>
			<li>UTX <B>Performance</B> (Q3 88): 
				Performance evaluation on both PN and NP product lines. 
				Development of tools for performance evaluation.
				Wrote application notes on use of directly connected 
				interrupts.
				Eliminating jitter and drift errors in timer facilities.
			<li>UTX 2.1[AB] <B>Maintenance and Testing</B> (Q2 88): 
				Bugfixing in NFS, timers, buffer cache. 
				System V compatibility.
			<li>UTX 2.1 (87-88) <B>Performance</B>: 
			    Member of the first Performance Team in Gould UNIX Development,
			    responsible for tightly coupling performance issues
			    with development. PN product line.
			    Collected and automated benchmark suite. 
			    Wrote real-time UNIX benchmarks. 
			    Investigated performance problems in system baselines: 
			    buffer cache problems (improved write throughput by 
			    >400%), memory layout. 
			    Optimized and inlined critical kernel routines. 
			<li><B>Real Time UNIX</B> (85-87): 
			    Designed and implemented real-time scheduler 
			    on a dual CPU system: 
			    fixed-priority non-preemptive scheduling, CPU targetting, 
			    fast suspend/resume. 
			    Tested high 
			    speed clock facility. 
			    Devised configuration control system based
			     on hardlinks, parallel trees, and 
			    restricted environments wrapped around RCS (see publications).
			</ul>

		</ul>

	    <dt>1986: <b>Programmer</b>, Systemes Videotex FORMIC, Saint Laurent, Quebec. <dd>
		<ul>	
		<li>NAPLPS videotex - graphical editor. 
		<li>Implemented public access graphical database system. 
		<li>Developed system for managing multilingual 
		    (English/French/...) versions of software. 
		<li>Wrote graphics, keyboard, and mouse drivers 
		    for IBM PC compatibles.
		<li>Designed multiport serial card.
		</ul>

	    <dt>1982-1986: <b>UNIX System Manager</b>,<dd> 
		Electrical Engineering Undergraduate Computer Lab, 
		McGill University. 
		PDP-11/40 and CODATA MC68000 based machines running UNIX V7,
		Matrox graphics and image processing systems.

	    <dt>1981-1984: <b>Computer Operator/Programming Consultant</b>,<dd> 
		McConnell Computing Facility, McGill University. 
		IBM 370 assembly, COBOL, FORTRAN, PASCAL, PL/1.

	    <dt>Summer 1979: <b>Student Programming Assistant</b>, Concordia University. <dd>
		FORTRAN graphics programming of wireframe aircraft models 
		on a PDP-11/40 running RT-11v4, and on CDC NOS.

	    </dl>

	<h2>Other Training</h2>

	    <ul>
	    <li>Intel <b>First Line Manager Training</b>. June 1993
	    <li><b>Transaction Processing</b>,
		Stanford Western Institute of Computer Science class
		taught by Jim Gray, June 1992.
	    <li><b>High Performance Compilers</b>. 
		Class given by Prof. Michael Wolfe of the Oregon Graduate Institute 
		in Portland, May 1991.
	    <li><b>Software Testing</b>. 
		Class given by Prof. Roy Campbell 
		    of the University of Illinois at Urbana-Champaign, 
		at Gould CSD Urbana. 
		Led to "Certificate in Software Testing". June 1986.
	    </ul>

	<h2>Publications</h2>

	    <ul>

	    <li>Andy Glew, <b>"Boxes, Links, and Parallel Trees: Elements of a
	    Configuration Management System"</b>, USENIX Workshop Proceedings,
	    Software Management. USENIX Association, April 3-4, 1989, New
	    Orleans, Louisiana.


	    <li>Andy Glew, <b>"An Empirical Evaluation of ORed Indexing"</b>, ACM
	    SIGMETRICS Performance Evaluation Review, Vol. 17 No. 2, January 1990.

	    <li>Andy Glew and Wen-Mei Hwu, <b>"Snoopy Cache Test-and-test-and-set
	    Without Excessive Bus Contention"</b>,
	    Computer Architecture News, Vol.18, No. 2, June 1990, pp. 25-32.

	    <li>Andy Glew and Mandar Joshi, <b>"Improved Framebuffer Memory Type"</b>,
	    Intel Design Technology Conference, 1994.

	    <li>Andy Glew and Pohua Change, <b>"P6 Compiler Optimizations"</b>,
	    Intel Software Development Conference, 1993.

	    </ul>

	<h2>Awards</h2>

	    <DL>
	    <DT>Intel Acheivement Award, 1996<DD>
		for the Pentium Pro Processor 
		Dynamic Execution microarchitecture;
		shared with Bob Colwell, Dave Papworth, Glenn Hinton,
		and Mike Fetterman.

	    <DT>Divisional Recognition Award, 1996<DD>
		Intel Israel Design Center (IDC),
		for the creativity and driving of Intel Architecture
		Microprocessor Multimedia Extension (IA-MMX)
		Architecture definition;
		shared with many other members of the MMX team
		led by Alex Peleg and Uri Weiser.
	    </DL>

	<h2>Patents</h2>

	    Co-inventor on more than 100 Intel patent disclosures filed
	    and approved for submission to patent office,
	    more than 40 of which have been submitted to patent office.

	    At last count 7 patents have been awarded by US patent office.

	<h2>Personal</h2>

	    <ul>
	    <li> Languages: English and French.
	    <li> Societies: IEEE Computer Society,
		    ACM SIGARCH, SIGMETRICS, SIGMICRO, SIGOPS, SIGPLAN. 
		    Standards balloting for FUTUREbus+ and SCI. 
	    <li> Citizenship: Canadian. 
		    US Permanent Resident Visa.
	    </ul>


	<h2>References</h2>

	    <P>
	    The following is a coworker in Intel's Microcomputer Research Labs,
	    who also worked with me through much of P6:
	    <ul>
	    <li>Wen-Hann Wang, Manager, Platform (Cache and Memory Subsystem) research section,
		Intel Microcomputer Research Labs.
		Intel Corporation,
		2111 NE 25th Ave
		mailstop JF1-91
		Hillsboro, OR 97124-5961
		503-264-4681.
		<code>wang@ichips.intel.com</code>
	    </ul>

	    <p>
	    The following were my managers at Intel during P6:
	    <ul>
	    <li>Bob Colwell, Manager, P6 Architecture,
		503-264-4550, <code>colwell@ichips.intel.com</code>
	    <li>Dave Papworth, Manager, P6 Macroarchitecture
		503-264-4603, <code>papworth@ichips.intel.com</code>
	    </ul>
	    Both are at:
		Intel Corporation,
		2111 NE 25th Ave
		mailstop JF1-19
		Hillsboro, OR 97124-5961.

	    <p>
	    My MS advisor:
	    <ul>
	    <li>Professor Wen-Mei Hwu, 
		256 CSRL, MC 228,
		1308 W Main,
		Urbana, IL 61801,
		    (217) 244-8270,
		    <code>hwu@crhc.uiuc.edu.</code>
	    </ul>

	    <p>
	    The following Intel luminaries have agreed 
	    to provide phone references as to my character.
	    They're too busy and not allowed to write to write letters
	    of reference, but I wanted to include their names here as blatant name dropping:
	    <ul>
	    <li>John Crawford, Intel Fellow, P7 Manager.
		408-765-4575,
		<code>John_H_Crawford@ccm.sc.intel.com</code>
	    <li>Fred Pollack, Intel Fellow, Manager,
		Microprocessor Architecture and Planning.
		503-264-4383, <code>Fred_Pollack@ccm.jf.intel.com</code>
	    <li>Pete MacWilliams, Intel Fellow, Intel Server Division
		503-696-8424, <code>Pete_MacWilliams@ccm.jf.intel.com</code>
	    </ul>


	    <p>
	    Previous employer:
	    <ul>
	    <li>Steve Bunch, Manager, Urbana Design Center, 
		Motorola Microcomputer Division, 1101 E. University, 
		Urbana, Illinois, 61801. 217-384-8500. <code>srb@urbana.mcd.mot.com.</code>
	    <li>Scott Preece, Manager, Distributed Systems Group, 
		Urbana Design Center, Motorola Microcomputer Division, 
		1101 E. University, Urbana, Illinois, 61801. 217-384-8500. 
		<code>preece@urbana.mcd.mot.com.</code>
	    </ul>

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